The present invention generally relates to semiconductor devices including DRAM integrated circuit devices and methods of producing the semiconductor devices, and, more particularly, to a semiconductor device and a DRAM integrated circuit device that have a multi-layer wiring structure with contact plugs or via plugs having different depths.
At present, a semiconductor device normally has a multi-layer wiring structure that is flattened by a CMP (chemical mechanical polishing) technique to connect with a number of elements formed on a substrate. In a typical multi-layer wiring structure, wiring layers and interlayer insulating films are alternately formed, and wiring layers or conductive portions having an interlayer insulating film in between are electrically connected to each other with a contact plug or the like. The contact plugs formed in such a multi-layer wiring structure have different depths depending on the conductive portions to be connected, such as the locations of diffusion regions or gate regions.
Particularly, in the case of a minute DRAM integrated circuit device or an integrated circuit device including DRAMs, scattering of the charge accumulated in the memory cell capacitors should preferably be restricted, and a sufficiently long refreshing period should be secured. To so do, it is necessary to restrict the occurrence of lattice defects in the diffusion regions in the MOSFETS that form the memory cell transistor. Therefore, it is also necessary to reduce the impurity concentration in the diffusion regions. Contact plug to be in contact with diffusion regions with low impurity concentration are preferably made of polysilicon of the same conductivity type, so as to obtain low contact resistance with respect to Si.